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PM3351

SINGLE PORT FAST ETHERNET SWITCH

PMC-Sierra 

DATA SHEET

PMC-970113

ISSUE 3

PM3351 ELAN 1X100

SINGLE PORT FAST ETHERNET SWITCH

MRD*

1

O Memory read enable. This output signals the external memory banks that a

read is being performed and data should be output on the MDATA[31:0] lines

from the specified address. The MRD* output may be tied to the OE* inputs of

standard memory devices.

MWR[3:0]*

4

O Memory write enables, used by the PM3351 to enable the data presented on

individual byte lanes of MDATA[31:0] to be individually written to memory.

MWR[0]* corresponds to MDATA[7:0], MWR[1]* corresponds to MDATA[15:8],

and so on. The MWR[3:0]* outputs should be connected to the appropriate

byte write enables.

MGWE*

1

O Gobal memory write enable. This signal is used to signal that a write access is

occurring, and should be connected to the WE* inputs of dual CAS

asynchronous DRAM devices.

NOTE- can be left as a no-connect output if not using DRAM

MRDY*

1

I

Memory ready input. If an external memory timing generator is used, it can be

connected to the MRDY* input to force the PM3351 to insert wait states into

memory accesses. If the MRDY* line is deasserted, the PM3351 will hold the

MADDR[15:0], MCS[3:0]*, MRD* and MWR[3:0]* lines at their present values

(as well as MDATA[31:0] for memory writes).The MRDY* input is only sampled

by the PM3351 when performing an SRAM-type access; it is ignored for all

other memory types.

MINTR*

This feature is not tested as part of the fuctional test program of the device.

Therefore, MRDY* must be tied low (to logic 0) to ensure correct operation.

1

I

Local interrupt input. The MINTR* may be used to provide an interrupt input to

the ELAN 1x100 in special applications. If the MINTR* input is not used it

should be tied HIGH.

For improved noise immunity this input buffer uses a Schmitt trigger.

Clock Inputs and Outputs

Signal Name

SYSCLK

MEMCLK

CLK25

Size

1

1

1

Type

I

O

O

Description

50 MHz master device clock input, This should be driven by a 50 MHz

symmetrical clock source with a duty cycle between 40% and 60%. It is re-timed

and driven out on the MEMCLK line, and is also used in the internal device

logic.

For improved noise immunity this input buffer uses a Schmitt trigger.

50 MHz clock derived from SYSCLK; supplies the re-timed 50 MHz clock (input

on the SYSCLK pin) to external devices.

25 MHz clock output. The 50 MHz input clock is internally divided by two and

output as a symmetrical 25 MHz clock on the CLK25 output; this clock may be

used as a clock reference input to an external PHY device.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

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