CXD2719Q Просмотр технического описания (PDF) - Sony Semiconductor
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CXD2719Q Datasheet PDF : 59 Pages
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CXD2719Q
3. Reset Circuit
[Relevant pins] XRST, XTLI, XTLO
This LSI must be reset after the power is turned on.
Reset is done by setting the XRST pin Low for 1/fs or more after the supply voltage satisfies the recommended
operating condition, and the crystal oscillator clock of the XTLI and XTLO pins or the external clock input from
the XTLI pin is correctly applied. (See "AC Characteristics".)
4. Serial Audio Interface (SIF)
[Relevant pins] SI, BCK, LRCK, XS24, XMST
Serial data is used for the external communication of the digital audio data. The CXD2719Q has only one input
system, and 2 channels of data are input each sampling cycle. Either the 32-bit clock mode or the 24-bit clock
mode can be selected. In master mode, the mode is fixed to the 32-bit clock mode.
(1) Pin Configuration (The pins shown in the table below are assigned to the SIF.)
Symbol
SI
BCK
LRCK
XS24
XMST
I/O
Function
I Serial input; taken with synchronized to BCK.
I/O
BCK I/O; either 32-bit clock mode (64fs) or 24-bit clock mode (48fs). BCK output supports
32-bit clock mode only.
I/O LRCK I/O (1fs).
SIO slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot.
I Valid only in slave mode. Set High in master mode.
Do not switch between High and Low during DSP operation.
I
BCK, LRCK master mode/slave mode switching input.
Low: master mode; High: slave mode.
Table 4-1. Pin Configuration
(2) Operation Modes
The LRCK/BCK mode can be selected by the setup register settings as follows. (See "6. Setup Register".)
LRCK/BCK Mode Setting
Setup register
SQC15
SQC14
SQC13
Function
LRCK format
LRCK polarity selection
BCK polarity selection relative to LRCK edge
Valid only in slave mode. Fix to "0" in master
mode.
Contents
"0": normal, "1": IIS
"0": Lch "H", "1": Lch "L"
"0": edge ↓, "1" : edge ↑
Table 4-2. LRCK/BCK Mode Setting
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