Philips Semiconductors
Single-chip colour CRT controller
(FTFROM)
PARAMETER
CLKO, F1/F6, R, G, B, VDS
FS/DDA, OD (notes 6, 7 and Fig.6)
CLKO HIGH time
CLKO LOW time
CLKO rise and fall times
CLKO HIGH to R, G, B, VDS change
R, G, B, VDS valid to CLKO rise
CLKO HIGH to R, G, B, VDS valid
CLKO HIGH to R, G, B, VDS floating
after OD fall
Skew between outputs R, G, B, VDS
R, G, B, VDS rise and fall times
CLKO HIGH to R, G, B, VDS active
after OD rise
CLKO HIGH to FS/DDA change
FS/DDA valid to CLKO rise
F1 HIGH time (note 8)
F1 LOW time (note 8)
F6 HIGH time
F6 LOW time
OD to CLKO rise set-up
OD to CLKO HIGH hold
MEMORY ACCESS TIMING
(notes 9, 10 and Fig.7)
UDS, LDS, AS
Cycle time
UDS HIGH to bus-active for address output
Address valid set-up to AS fall
Address valid hold from AS LOW
Address float to UDS fall
AS LOW to UDS fall delay
UDS, LDS HIGH time
UDS, LDS LOW time
AS HIGH time
AS LOW time
Product specification
SAA5355
SYMBOL MIN.
TYP.
MAX. UNIT
tCLKH
25
−
tCLKL
15
−
tCLKr
−
−
tCLKf
tVCH
10
−
tVOC
10
−
tCOV
−
−
−
ns
−
ns
10
ns
−
ns
−
ns
60
ns
tFOD
0
−
30
ns
tVS
−
−
20
ns
tVr, tVf
−
−
30
ns
tUOD
tDCH
tDOC
tF1H
tF1L
tF6H
tF6L
tODS
tODH
0
−
60
ns
10
−
60
ns
5
−
−
ns
−
500
−
ns
−
500
−
ns
−
83
−
ns
−
83
−
ns
−
−
45
ns
−
−
0
ns
tcyc
−
500
−
ns
tSAA
75
−
−
ns
tASU
20
−
−
ns
tASH
20
−
−
ns
tAFS
0
−
−
ns
tATD
50
−
−
ns
tHDS
220
−
−
ns
tLDS
200
−
−
ns
tHAS
125
−
−
ns
tLAS
320
−
−
ns
March 1986
9