LC74201JE Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC74201JE

Single Chip MPEG Decoder

SANYO -> Panasonic 

LC74201JE

1. Parallel interface

The parallel interface uses the following two input pins and eight I/O pins.

• AS/DS pin (pin 43: input): Address/data select input. low = address; high = data.

• STB pin (pin 44: input): Strobe signal input for address input and data I/O.

• AD0 pin (pin 45 : I/O): Address input and data I/O

AD1 pin (pin 46 : I/O): Address input and data I/O

AD2 pin (pin 47 : I/O): Address input and data I/O

AD3 pin (pin 48 : I/O): Address input and data I/O

AD4 pin (pin 49 : I/O): Address input and data I/O

AD5 pin (pin 50 : I/O): Address input and data I/O

AD6 pin (pin 51 : I/O): Address input and data I/O

AD7 pin (pin 52 : I/O): Address input and data I/O

Note: The address cannot be read.

Address and data transfer procedures

The command address is assigned to the lowest seven bits of the address. The most significant bit (AD7) is used to

specify write or read. The address can only be written. It cannot be read.

• Writing data

Set the AS/DS pin (pin 43) at low level to specify address input. Specify the address in the lowest seven bits. Set the

top bit to 0. Set the STB pin (pin 44) at high level to cause the LSI to read the address. The parallel interface mode

can be configured to read input using a choice of three different timings.

— Data read at rising edge of STB pin input.

— Data read at falling edge of STB pin input.

— Data read while STB pin input at high level.

0

Set the AS/DS pin (pin 43) at high level to specify data input. Set the STB pin (pin 44) at high level to cause the LSI

to read the data.

No. 5761-15/21

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