STV1602A
Figure 22 : Phase Relation of Parallel Clock, Data and EVR Voltage Level
Parallel clock
Parallel data
V OH
EVR output voltage
Figure 23 : Parallel Clock Data Output Circuit
EVR 21
1kΩ
PCK 19
1kΩ
D0 18
1kΩ
STV1602A
D9 9
1kΩ
V EE
0.1µF
Figure 24 : A Circuit Example to Disable Parallel
Clock
DPR 35
CMOS inverter
10kΩ
EVR 6
PCK 21
STV1602A
1kΩ
1kΩ
VEE
10kΩ
0.1µF
0.1µF
8. VCO temperature compensation and oscil-
lation frequency adjustment.
VCO oscillation frequency depends on the tem-
perature as shown in Figures 29 and 30 ”Repre-
sentative characteristics example”. Within the
normal range of operation, frequency increases
V OL
with temperature.
FV pin voltage remains almost constant regardless
of temperature.
Figure 25 shows an example of a temperature
compensation circuit using a diode (transistor with
C-B diode short-circuited) and a resistor between
FV and VEE.
PLL pull-in range (signal frequency 270, 177 and
143MHz) are given by Figures 32, 33 and 34.
9. VCO free running frequency adjustment
VCO free running frequency adjustment is per-
formed at room temperature.
If TN1 is set High, VCO is free running. Wait for 5
to 10 minutes after turning power supply ON (warm
up time).
While monitoring PCK (Pin 19) output, adjust the
signal frequency (within ±1%) with the variable
resistor connected between FV and VEE.
Figure 25 : VCO Temperature Compensation
and Free Running Frequency Ad-
justment
TN1
6
10µF
STV1602A
FV
PCX
36
19
22kΩ
Small signal
transistor
10kΩ
Frequency monitor
1kΩ
VEE
18/22