HT16270 Просмотр технического описания (PDF) - Holtek Semiconductor
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HT16270 Datasheet PDF : 17 Pages
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W R ,R D 90%
C lo c k
50%
10%
tf
tC L K
tr
tC L K
Figure 1
-V DD
GND
DB
W R ,R D
C lo c k
CS
W R ,R D
C lo c k
50%
tsu 1
tC S
th 1
50%
F IR S T
C lo c k
LA S T
C lo c k
Figure 3
-V DD
GND
-V DD
GND
V A L ID D A T A
50%
ts u
th
50%
Figure 2
HT16270
V DD
GND
V DD
-G N D
Functional Description
Display memory - RAM structure
The static display RAM is organized into 256´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be
accessedbytheREAD,WRITEand
READ-MODIFY-WRITE commands. The fol-
lowing is a mapping from the RAM to the LCD
patterns.
C O M 15 C O M 14 C O M 13 C O M 12
SEG 0
3
SEG 1
7
SEG 2
11
SEG 3
15
Time base and watchdog timer - WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will remain at
logic low level until the CLR WDT or the IRQ
DIS command is issued.
COM 3 COM 2 COM 1 COM 0
0
4
8
12
A d d r e s s 8 B its
(A 7 , A 6 , ...., A 0 )
S E G 63
255
252
A ddr
D3
D2
D1
D0
D a ta
A ddr
D3
D2
D1
D0
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
8
April 21, 2000
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