UT1750AR12GPC Просмотр технического описания (PDF) - Aeroflex UTMC

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UT1750AR12GPC

RISC Microprocessor

Aeroflex UTMC 

This double-buffering process allows transmitting contiguous

serial data streams. The process of alternately loading the

Transmitter Buffer Register with new data and then reading the

transmitter status from the STATUS continues until completion

of all serial data transmission.

UART Receiver Operation

The UT1750AR’s internal UART has one register associated

with the receive function. This register is the UART Receiver

Buffer Register (RBR). The least significant byte of the RCVR

contains the received serial data. The System Status Register

(STATUS) contains error information about the serial data in

the RCVR. These four error bits are (1) Bit 7, the Receiver Error

(RE), which is the logical OR combination of the other three

error bits; (2) Bit 6, an Overrun Error (OE); (3) Bit 5, a Framing

Error (FE); and (4) Bit 4, a Parity Error (PE). An additional

status bit for the Receiver is the Data Ready (DR) bit. DR is the

least significant bit of the STATUS.

When the UT1750AR is ready to receive serial data through the

internal UART, it must poll the STATUS to determine when the

Data Ready (DR) bit transitions from a low to a high to signify

that the UART has indeed received a serial transmission. When

DR = 1, the system programmer reads the RCVR by executing

an Input instruction. The INR instruction takes the eight bits of

received data in the RCVR and places this data in the least

significant byte of the destination register specified in the

instruction.

When the UT1750AR is finished executing the Input

instruction, the system programmer can then determine the

validity of the message by testing the RE bit. After the

programmer has checked for a valid message, the data can be

stored. If the UT1750AR is to receive more data through the

UART, the programmer must return to polling the STATUS to

determine the reception of the next valid serial transmission.

1750 CONSOLE MODE OF OPERATION

The UT1750AR supports a defined Console mode of operation

when operating as a MIL-STD-1750 processor. The Console

mode of operation is a unique mode of operation that allows the

system programmer to connect the UT1750AR directly to a

programmer’s console. The actual console can be any type of I/

O device, such as a computer terminal, that allows the

programmer to interface with the UT1750AR’s internal UART.

While operating the UT1750AR in the Console mode, the

programmer can (1) examine and modify the UT1750AR’s

internal registers; (2) examine and modify the contents of the

Operand memory; (3) examine and modify the contents of the

RISC memory; (4) examine and modify the contents of the I/O

subsystems; (5) continue the execution of a 1750 program; and

(6) have the UT1750AR begin program execution from any

address.

The CONSOLE input is a discrete input to the UT1750AR and

is read as bit 3 in the System Status Register (STATUS). The

definition of this input is not inherent to the UT1750AR, but is

defined only by the programming within the RISC PROMs.

Since, as with many other operational features of the

UT1750AR, the Console mode is a function of the programming

in the RISC PROMs, the user can tailor the UT1750AR’s

Console mode to a specific application. For example, the user

can modify the Console mode program in the RISC PROMs so

when the UT1750AR executes this code, it performs a system-

level test. When complete, the UT1750AR reports the results to

the programmer’s console where the user can ascertain the

functional integrity of the system.

UARTOUT

12 MHz I/P

FOR UART

UT1750AR

TIMCLK

UARTIN

SERIAL

BUS

DRVR

SERIAL

BUS

RCVR

Figure 30. Serial Data Bus Interface to the UT1750AR

30

SERIAL RS-232 BUS --

9600 BAUD

EIGHT DATA BITS,

ONE STOP BIT

AND ODD PARITY

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