USS344 Просмотр технического описания (PDF) - Agere -> LSI Corporation
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USS344 Datasheet PDF : 54 Pages
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USS-344 QuadraBus
Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9
June 2001
PCI Registers (continued)
Table 41. BIST Register (0Fh)
BIST is not supported by the USS-344.
Bits
7:0
BIST
Field
Read/Write
R
Reset/Description
00h
Table 42. Base Address Register 0 (10h—13h)
The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device.
As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K
(212) memory size.
Bits
31:0
Field
BAR 0
Read/Write
R/W
Reset/Description
Lower 12 bits are read only. Upper
20 bits are read/write.
Table 43. Base Address Register 1, 2, 3, 4, 5 (14h—17h), (18h—1Bh), (1Ch—1Fh), (20h—23h), (24h—27h)
These Base Address registers are unused by the USS-344 device.
Bits
31:0
Field
BAR 1—5
Read/Write
R
Reset/Description
00000000h
Table 44. Cardbus CIS Pointer Register (28h—2Bh)
Cardbus CIS pointer not required for the USS-344.
Bits
31:0
Field
Read/Write
CardBus CIS Pointer R
Reset/Description
00000000h
Table 45. Subsystem Vendor ID Register (2Ch—2Dh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
15:0
Field
Read/Write
Subsystem Vendor ID R/W
Reset/Description
11C1h
Table 46. Subsystem ID Register (2Eh—2Fh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
15:0
Field
Subsystem ID
Read/Write
R/W
Reset/Description
5803h
18
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