DS21Q554 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS21Q554

Quad T1/E1 Transceiver (5V), Quad T1/E1 Transceiver (3.3V)

Dallas Semiconductor -> Maxim Integrated 

DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet

POWER SUPPLY DE-COUPLING

In a typical PCB layout for the DS21x5y, all of the VDD pins will connect to a common power plane and all

the VSS lines will connect to a common ground plane. There are three recommended methods for de-

coupling shown below in both schematic and pictorial form. As shown in the pictorials, the capacitors

should be symmetrically located about the device. The first shown in figure 3 uses standard capacitors,

two 33uf tantalums, two .33uf ceramics and two .01uf ceramics. The second method shown in figure 4

uses a single 68uf tantalum, two .33uf ceramics and two .01uf ceramics. The third method shown in figure

5 uses only four capacitors, two 1.5uf MLC and two .01uf ceramics. The 1.5uf is an MLC (Multi Layer

Ceramic) type. The MLC construction is a low inductance type, which allows a smaller value of

capacitance to be used. Since VDD and VSS signals will typically pass vertically to the power and ground

planes of a PCB, the de-coupling caps must be placed as close to the DS21Qx5y as possible and routed

vertically to power and ground planes.

De-coupling scheme using standard tantalum caps. Figure 3

VDD

VDD

33 .33 .01

DS21Qx5y

33 .33 .01

33

33

.33 DS21Qx5y .33

.01

.01

De-coupling scheme using single 68uf cap. Figure 4

VDD

VDD

68 .33 .01

DS21Qx5y

.33 .01

68

.33 DS21Qx5y .33

.01

.01

De-coupling scheme using MCL caps. Figure 5

VDD

VDD

1.5 .01

DS21Qx5y

1.5 .01

1.5

1.5

.01 DS21Qx5y .01

All capacitor values in figures 3, 4 and 5 are in uf.

December 29, 1998

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