ML6411 Просмотр технического описания (PDF) - Micro Linear Corporation

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ML6411

Programmable Video Digitizer with Selectable Gain and Clamps

Micro Linear Corporation 

TIMING CONTROL

The ML6411 operates in master mode where all internal

timing is derived from the clock input at the CLK pin.

Figure 2 provides timing diagrams for both the Dual

Composite and Y/C modes. Note that the REF OUT pin

provides the internal timing to the REF IN pin. These pins

are shorted together for normal operation.

Serial Bus Timing. Figure 3 provides timing of serial bus

mode. Figure 4 provides a detailed timing for device,

register, and data insertion to the control registers. As

ML6411

shown in Figure 1, there are six independent 5-bit registers

in the Control Block. To load a register, the 3-bit address is

loaded in first followed by the 5-bit data values and a

dummy bit. This is a total of 9-bits to load a register with

the last bit being a dummy bit. Note that all of the registers

can be loaded in succession before the STOP condition is

enabled.

The CLKDIV function provides an internal divide-by-2

clock. This function is enable via control register.

VIN

tds

CLK

SAMPLE

N

SAMPLE

N +1

SAMPLE

N +2

SAMPLE

N +3

SAMPLE

N +4

tcph

tcpl

S/H CHANNEL A

SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD

S/H CHANNEL A

OEC

OEY

Y<7:0>

C<7:0>

CV1<7:0>

CV2<7:0>

SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD

Yn -3

Cn -3

tod

Yn -2

Cn -2

toe

Yn -1

Cn -1

Yn

Cn

tho

tdo

Figure 2. Y/C and Dual CV Mode

Yn +1

Cn +1

Yn +2

Cn +2

17

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