74HC/HCT192 Просмотр технического описания (PDF) - Philips Electronics

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производитель

74HC/HCT192

Presettable synchronous BCD decade up/down counter

Philips Electronics 

Philips Semiconductors

Presettable synchronous BCD decade

up/down counter

Product specification

74HC/HCT192

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU,

CPD removal time and output transition times.

The shaded areas indicate when the input is permitted

to change for predictable output performance.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.11 Waveforms showing the data input (Dn) to parallel load input (PL) set-up and hold times.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.12 Waveforms showing the data input (Dn), parallel load input (PL) and the master reset input (MR) to the

terminal count outputs (TCU, TCD) propagation delays.

December 1990

12

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