LTC1412 Просмотр технического описания (PDF) - Linear Technology

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LTC1412

12-Bit, 3Msps, Sampling A/D Converter

Linear Technology 

LTC1412

APPLICATIONS INFORMATION

5V

VIN

VOUT

LT1019A-2.5

ANALOG INPUT

1 AIN+

2 AIN–

LTC1412

3

VREF

4

REFCOMP

10µF

5

AGND

1412 F08b

Figure 8b. Using the LT1019-2.5 as an External Reference

The VREF pin can be driven with a DAC or other means

shown in Figure 9. This is useful in applications where the

peak input signal amplitude may vary. The input span of

the ADC can then be adjusted to match the peak input

signal, maximizing the signal-to-noise ratio. The filtering

of the internal LTC1412 reference amplifier will limit the

bandwidth and settling time of this circuit. A settling time

of 5ms should be allowed for after a reference adjustment.

LTC1450

ANALOG INPUT

1.25V TO 3V

DIFFERENTIAL

1 AIN+

2 AIN–

LTC1412

1.25V TO 3V 3 VREF

4

REFCOMP

10µF

5

AGND

1412 F09

Figure 9. Driving VREF with a DAC

0

– 20

– 40

– 60

– 80

–100

VSS

VDD

DGND

–120

1k

10k

100k

1M

10M

RIPPLE FREQUENCY (Hz)

1412 G08

Figure 10. CMRR vs Input Frequency

mode voltage. THD will degrade as the inputs approach

either power supply rail, from – 86dB with a common

mode of 0V to –75dB with a common mode of 2.5V

or – 2.5V.

Full-Scale and Offset Adjustment

Figure 11a shows the ideal input/output characteristics for

the LTC1412. The code transitions occur midway between

successive integer LSB values (i.e., – FS/2 + 0.5LSB,

– FS/2 + 1.5LSB, – FS/2 + 2.5LSB,...FS/2 – 1.5LSB, FS/2 –

0.5LSB). The output is two’s complement binary with

1LSB = FS – (– FS)/4096 = 5V/4096 = 1.22mV.

111...111

111...110

111...101

Differential Inputs

The LTC1412 has a unique differential sample-and-hold

circuit that allows rail-to-rail inputs. The ADC will always

convert the difference of AIN+ – (AIN–) independent of the

common mode voltage. The common mode rejection

holds up to extremely high frequencies, see Figure 10. The

only requirement is that both inputs cannot exceed the

AVDD or AVSS power supply voltages. Integral nonlinearity

errors (INL) and differential nonlinearity errors (DNL) are

independent of the common mode voltage, however, the

bipolar zero error (BZE) will vary. The change in BZE is

typically less than 0.1% of the common mode voltage.

Dynamic performance is also affected by the common

000...010

000...001

000...000

FS – 1LSB

FS – 1LSB

INPUT VOLTAGE (V)

1412 F11a

Figure 11a. LTC1412 Transfer Characteristics

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figure 11b

shows the extra components required for full-scale error

adjustment. Zero offset is achieved by adjusting the offset

applied to the AIN– input. For zero offset error apply

12

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