MT90500AL Просмотр технического описания (PDF) - Mitel Networks

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MT90500AL

Multi-Channel ATM AAL1 SAR

Mitel Networks 

MT90500

Table 2 - Secondary UTOPIA Bus Pins

Pin #

Pin Name

I/O

Type

Description

70, 71, 72, 73, STXDATA[7:0] I

74, 75, 76, 77

TTL PU Secondary UTOPIA transmit data bus. Byte-wide data driven from the external

SAR to the MT90500. Bit 7 is the MSB.

69

STXSOC

I

TTL PU Secondary UTOPIA transmit start of cell signal. Asserted by the external SAR

device when STXDATA[7:0] contains the first valid byte of the cell.

68

STXEN

I

TTL PU Secondary UTOPIA transmit data enable. Active LOW signal asserted by the

external SAR during cycles when STXDATA[7:0] contains valid cell data.

67

STXCLAV

O

5V, 4mA Secondary UTOPIA transmit cell available indication signal. For cell level flow

control, STXCLAV is asserted by the MT90500 to indicate to the external SAR that

the MT90500 can accept the transfer of a complete cell.

85

STXCLK

I

TTL PU Secondary UTOPIA transmit clock, which can run at up to 25 MHz. Data transfer &

synchronization clock provided by the external SAR to the MT90500 for

transmitting data over STXDATA[7:0].

Note: MT90500 Secondary UTOPIA port emulates a PHY device for connection to an external SAR (ATM-layer device).

Refer to Figure 63 on page 139 for implementation details regarding the interface between the MT90500 and an external AAL5 SAR.

Table 3 - Microprocessor Bus Interface Pins

Pin #

Pin Name

I/O

Type

Description

37

Intel/Motorola

I

TTL PU Intel interface (1) / Motorola interface (0)

36

IC

I

TTL PU Internal connection (must be HIGH).

203

CS

I

TTL PU Active LOW chip select signal.

237

WR/R\W

I

TTL PU Active LOW Write Strobe (Intel) / Read-Write (Motorola).

239

RD/DS

I

TTL PU Active LOW Read Strobe (Intel) / Active LOW Data Strobe (Motorola).

238

RDY/DTACK

O

5V, 4mA Ready (Intel) / Data Transfer Acknowledge (Motorola). Acts as active LOW

pseudo-open-drain in Motorola mode (DTACK, see Figure 53 on page 126).

Acts as normal output in Intel mode, high impedance when CS is HIGH (RDY).

84

INT

O 5V, 4mA SR Active LOW interrupt line.

(Open-Drain)

223, 222, 219,

218, 217, 216,

215, 214, 212,

211, 210, 209,

208, 206, 205,

204

D[15:0]

I/O

TTL PU / CPU data bus.

5V, 4mA SR

184

AEM

I

TTL PU Access External Memory - CPU accesses external memory when HIGH

(internal memory and registers when LOW).

185, 186, 187,

188, 189, 190,

191, 192, 193,

194, 195, 196,

198, 199, 202

A[15:1]

I

TTL PU CPU Address lines A15-A1.

All microprocessor accesses to the device are word-wide, but addresses in

this document are given as byte-addresses. The virtual A[0] bit selects

between high and low bytes in a word.

Note: MT90500 TTL inputs are pulled up to the 5 Volt rail. See Table 76 on page 112.

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