SA9101 Просмотр технического описания (PDF) - South African Micro Electronic Systems

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SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

S -bit access

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In accordance with CCITT signalling requirements, the S bits of frame 13 and frame 15 of the

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CRC Multi-frame can be used to indicate received error submultiframes:

Submultiframe I status :

Submultiframe II status : Si15

no CRC error

:

CRC error

:

Si13

S =1

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S =0

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S -bits insertion can be done through the µP-interface(in non-Transparent and Extended

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Timeslot 0 Signalling Transparent modes) or, if enabled, automatically by the SA9101 without

any intervention of the microprocessor. In this case, the status information of received sub-

multiframe, is inserted in Si-bit position of the outgoing CRC-Multiframe. A third option is via

the system interface should the Timeslot 0 Transparent or Timeslot 0 Signalling Transparent

modes be selected.

Differences to Siemens ACFA (PEB2035 V4.1)

1. Automatic Force Resynchronisation feature for CRC mode,CR1B6 (Mode Register, bit

AFR), is not used because this feature is implemented in hardware to be carried out

automatically.

2. Sn bit stack

CR1B5 (Mode Register, bit ENSN) enables the Sn bit stack for both CRC Multiframe and

Double frame formats.

3. CRC Multiframe enable

CR1B3 (Mode Register, bit CRC) switches only between CRC Multiframe and DoubleFrame

formats. No need for CX1B7 (EMOD DFSN) to enable Sn bit stack in Double Frame format

due to point 2 above.

4. Service Word Condition Disable

CR9B7 (RC1.SWD) is not used. Always functions in Standard Operation mode, i.e. 3

consecutive incorrect service words will cause loss of synchronisation.

5. Select loss of Sync Condition

CR9B6 (RC1.ASY4) is not used. Always functions in Standard Operation Mode (according

to CCITT Rec.), i.e. 3 consecutive incorrect service words will cause loss of synchronisation.

6. Extended DMA Mode

CX1B1 (EMOD EDMA) is not used. The DMA facility must always read/write two

consecutive bytes. This is the only mode of operation therefore no selection is required.

7. Disable AIS to System Interface

CX1B0 (EMOD DAIS) is redefined. Siemens allowed for AIS selection for receive

transparent mode. However, in Receive transparent mode synchronisation may be lost and

therefore AIS is always disabled in the SA9101. This bit is redefined to provide a double

frame marker to provide synchronisation to the Double Frame format.

8. Unique feauture in Timeslot 0 Signalling Transparent Mode

The SA9101 is capable of recognising the frame alignment pattern and therefore will not

overwrite the Sn and Si information inserted externally (via DXI) in the desired bit locations

of the alternating timeslot 0 words.

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