MT89L86 Просмотр технического описания (PDF) - Mitel Networks
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MT89L86 Datasheet PDF : 40 Pages
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MT89L86
Stream Pair Selection Register - Read/Write
7
6
5
4
3
2
1
0
X
X SPA2 SPA1 SPA0 SPB2 SPB1 SPB0
Bit
Name
Description
5-3
SPA2-0 Stream Pair A selection. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPA2
0
0
0
0
1
1
1
1
SPA1
0
0
1
1
0
0
1
1
SPA0
0
1
0
1
0
1
0
1
Stream Pair A Connected
STi2 / STo2
STi3 / STo3
STi4 / STo4
STi5 / STo5
STi6 / STo6
STi7 / STo7
STi8 / STo8
STi9 / STo9
2-0
SPB2-0 Stream Pair B selection. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPB2 SPB1
SPB0 Stream Pair B Connected
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
STi2 / STo2
STi3 / STo3
STi4 / STo4
STi5 / STo5
STi6 / STo6
STi7 / STo7
STi8 / STo8
STi9 / STo9
These bits are only used when the Switching Configuration bits enable stream pair selection capability (SCB 1-0 =10) and the Input Data Rate
Selection bits enable 2 Mb/s operation (IDR-0 = 00). In all other modes, the contents of this register are ignored.
x=Don’t care
Figure 7 - Stream Pair Selection (SPS) Register
Frame Input Offset Register - Read/Write
7
6
5
4
3
2
1
0
OFB2 OFB1 OFB0 X
X
X
X
X
BIT
NAME
DESCRIPTION
7-5
OFB2-0 Offset Bits 2-0. These three bits define the time it takes the Serial Interface receiver to
recognize and store the first bit of the serial input streams; i.e., to start assuming a new
internal frame. The input frame offset can be selected to be up to 4 CK clock periods from
the time when frame pulse input signal is applied to the FR input.
OFB2 OFB1
OFB0 Number of Clock Periods
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
Normal Operation. No bit offsetting.
1
1
0
2
1
3
0
4
1
Reserved
0
Reserved
1
Reserved
If frame input offset operation is not required, this register should be cleared by the CPU during system initialization.
x=Don’t care
Figure 8 - Frame Input Offset (FIO) Register
19
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