MT89L86AN Просмотр технического описания (PDF) - Mitel Networks

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MT89L86AN

CMOS ST-BUS™ FAMILY Multiple Rate Digital Switch

Mitel Networks 

MT89L86

Advance Information

Identical

I/O

Rate

# of Input x

Output

Streams

STA bits used to

select subsections

of the Data

Memory

STA bits used to

select

subsections of the

Connection

Memory

Input Address pins used to

select individual

Connection and Data

Memory positions within the

selected subsection

2 Mb/s

8x8

STA2, STA1, STA0 STA2, STA1, STA0 A4, A3, A2, A1, A0

2 Mb/s

4x4

STA1, STA0

STA1, STA0

A4, A3, A2, A1, A0

2 Mb/s

16x8

STA3, STA2, STA1,

STA0

STA2, STA1, STA0

A4, A3, A2, A1, A0

4 Mb/s

4x4

STA1, STA0

STA1, STA0

A6, A4, A3, A2, A1, A0

4 Mb/s

8x4

STA2, STA1, STA0 STA1, STA0

A6, A4, A3, A2, A1, A0

8 Mb/s

2x2

STA0

STA0

A7, A6, A4, A3, A2, A1, A0

Nibble Switch

8x4

STA2, STA1, STA0 STA1, STA0

(2 Mb/s)

A6, A4, A3, A2, A1, A0 *

Table 6 - Use of STA Bits for Identical I/O Data Rate Operation

* - for Data Memory Read operations A0 is not required since two nibbles are provided per read access.

Different

I/O

Rate

Input x

Output

Streams

Config.

STA bits used

to select

Data

Memory

subsections

STA bits used Input Address pins used Input Address pins used

to select

to access individual to access individual

Connection

Data Memory

Connection Memory

Memory

positions within the

positions within the

subsections selected subsection selected subsection

2 Mb/s to

4 Mb/s

8x4 STA2, STA1, STA1, STA0 A4, A3, A2, A1, A0

STA0

A6, A4, A3, A2, A1, A0

2 Mb/s to

8 Mb/s

8x2 STA2, STA1, STA0

STA0

A4, A3, A2, A1, A0

A7, A6, A4, A3, A2, A1,

A0

4 Mb/s to

2 Mb/s

4x8 STA1, STA0 STA2, STA1, A6, A4, A3, A2, A1, A0 A4, A3, A2, A1, A0

STA0

8 Mb/s to

2 Mb/s

2x8 STA0

STA2, STA1, A7, A6, A4, A3, A2, A1, A4, A3, A2, A1, A0

STA0

A0

Table 7 - Use of STA Bits for Different I/O Data Rate Operation

Note:In rate conversion applications, Data Memory subsections have different sizes than Connection Memory subsections. This

implies that different address inputs are used to select individual positions within the subsections for each type of memory.

14

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