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Номер в каталоге(s) : M4A3-64/32-5VC48 M4A3-32/32-55VC48
Lattice
Lattice Semiconductor
Компоненты Описание : ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic

FEATURES

◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families

◆ Flexible architecture for rapid logic designs

    — Excellent First-Time-FitTM and refit feature

    — SpeedLocking performance for guaranteed fixed timing

    — Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆  High speed

    — 5.0ns tPD Commercial and 7.5ns tPD Industrial

    — 182MHz fCNT

◆ 32 to 512 macrocells; 32 to 768 registers

◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆ Flexible architecture for a wide range of design styles


Компоненты Описание : 32 macrocell CPLD

DESCRIPTION
The PZ3032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZP™) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design technique, the PZ3032 offers true pin-to-pin speeds of 8ns, while simultaneously delivering power that is less than 35µA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz.

FEATURES
• Industry’s first TotalCMOS™ PLD – both CMOS design and process technologies
• Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
• High speed pin-to-pin delays of 8ns
• Ultra-low static power of less than 35µA
• Dynamic power that is 70% lower at 50MHz than competing devices
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 2 clocks with Programmable polarity at every macrocell
• Support for complex asynchronous clocking
• Innovative XPLA™ architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Philips CAE tools
• ReProgrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
   – Programmable 3-State buffer
   – Asynchronous macrocell register preset/reset
Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources
• Available in both PLCC and TQFP packages

Компоненты Описание : MACH 4 CPLD Family High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system Programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM performance for guaranteed fixed timing
   — Central, input and output switch matrices
      for 100% routability and 100% pin-out retention
◆ High speed
   — 7.5ns tPD Commercial and 10ns tPD Industrial
   — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — Programmable polarity
   — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG in-system programming
   — PCI compliant (-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Bus-FriendlyTM inputs and I/Os
   — Programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
   — Supports HDL design methodologies with results optimized for MACH 4
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for in-system programmability support
      on PCs and automated test equipment
   — Programming support on all major programmers including Data I/O,
      BP Microsystems, Advin, and System General

Компоненты Описание : XC9536 In-System Programmable CPLD

Description

The XC9572 is  a high-performance CPLD  providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure2for the architecture overview.



Features

•  7.5 ns pin-to-pin logic delays on all pins

• fCNT to 125 MHz

•  72 macrocells with 1,600 usable gates

•  Up to 72 user I/O pins

•  5 V in-system Programmable (ISP)

-  Endurance of 10,000 program/erase cycles

-  Program/erase over full commercial voltage and temperature range

•  Enhanced pin-locking architecture

•  Flexible 36V18 Function Block

-  90 product terms drive any or all of 18 macrocells within Function Block

-  Global and product term clocks, output enables, set and reset signals

•  Extensive IEEE Std 1149.1 boundary-scan (JTAG) support

•  Programmable power reduction mode in each macrocell

•  Slew rate control on individual outputs

•  User Programmable ground pin capability

•  Extended pattern security features for design protection

•  High-drive 24 mA outputs

•  3.3 V or 5 V I/O capability

•  Advanced CMOS 5V FastFLASH technology

•  Supports parallel programming of more than one XC9500 concurrently

•  Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages


Номер в каталоге(s) : ATF1516AS-15QI160
Atmel
Atmel Corporation
Компоненты Описание : High Performance EE-Based CPLD

Description
The ATF1516AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel’s proven electrically erasable technology. With 256 logic macrocells and up to 164 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1516AS’s enhanced routing switch matrices increase usable gate count, and increase odds of successful pin-locked design modifications.

Features
• High Density, High Performance Electrically Erasable Complex Programmable Logic Device
   – 256 Macrocells
   – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
   – 160, 192, 208-pins
   – 10 ns Maximum Pin-to-Pin Delay
   – Registered Operation Up To 100 MHz
   – Enhanced Routing Resources
• Flexible Logic Macrocell
   – D/T/Latch Configurable Flip Flops
   – Global and Individual Register Control Signals
   – Global and Individual Output Enable
   – Programmable Output Slew Rate
   – Programmable Output Open Collector Option
   – Maximum Logic utilization by burying a register within a COM output
• Advanced Power Management Features
   – Automatic 3 mA Stand-By for “L” Version (Max.)
   – Pin-Controlled 4 mA Stand-By Mode (Typical)
   – Programmable Pin-Keeper Inputs and I/Os
   – Reduced-Power Feature Per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 160-pin PQFP, 192 PGA and 208-pin RQFP Packages
• Advanced EE Technology
   – 100% Tested
   – Completely ReProgrammable
   – 100 Program/Erase Cycles
   – 20 Year Data Retention
   – 2000V ESD Protection
   – 200 mA Latch-Up Immunity
• JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• 3.3 or 5.0V I/O pins
• Security Fuse Feature

Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• D - Latch Mode
• Combinatorial Output with Registered Feedback within any Macrocell
• Three Global Clock Pins
• ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
Programmable “Pin-Keeper” Option
• VCC Power-Up Reset Option
• Pull-Up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
   – Edge Controlled Power Down “L”
   – Individual Macrocell Power Option
   – Disable ITD on Global Clocks, Inputs and I/O

Номер в каталоге(s) : XC9572XL XC9572XL-10VQG44I
Xilinx
Xilinx Inc
Компоненты Описание : XC9572XL High Performance CPLD

The XC9572XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems.



http://www.xilinx.com/



http://www.xilinx.com/support/documentation/data_sheets/ds054.pdf


Компоненты Описание : 64 macrocell CPLD

DESCRIPTION

The PZ3064 CPLD (Complex Programmable Logic Device) is the second in a family of Fast Zero Power (FZP) CPLDs from Philips Semiconductors.



FEATURES

•Industry’s first TotalCMOSPLD – both CMOS design and process technologies

•Fast Zero Power (FZP) design technique provides ultra-low power and very high speed

•High speed pin-to-pin delays of 10ns

•Ultra-low static power of less than 50µA

•Dynamic power that is 70% lower at 50MHz than competing devices

•100% routable with 100% utilization while all pins and all macrocells are fixed

•Deterministic timing model that is extremely simple to use

•4 clocks with Programmable polarity at every macrocell

•Support for complex asynchronous clocking

•Innovative XPLAarchitecture combines high speed with extreme flexibility

•1000 erase/program cycles guaranteed

•20 years data retention guaranteed

•Logic expandable to 37 product terms

•PCI compliant

•Advanced 0.5µE2 CMOS process

•Security bit prevents unauthorized access

•Design entry and verification using industry standard and Philips CAE tools

•ReProgrammable using industry standard device programmers

•Innovative Control Term structure provides either sum terms or product terms in each logic block for:

Programmable 3-State buffer

–Asynchronous macrocell register preset/reset

Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources

•Available in PLCC, TQFP, and PQFP packages

•Available in both Commercial and Industrial grades



 


Atmel
Atmel Corporation
Компоненты Описание : High-performance CPLD

Description
The ATF1504BE is a high-performance, high-density complex Programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504BE’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.

Features
• High-performance Fully CMOS, Electrically-erasable Complex Programmable Logic Device
    – 64 Macrocells
    – 5.0 ns Pin-to-pin Propagation Delay
    – Registered Operation up to 333 MHz
    – Enhanced Routing Resources
    – Optimized for 1.8V Operation
    – 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V
    – SSTL2 and SSTL3 I/O Standards
• In-System Programming (ISP) Supported
    – ISP Using IEEE 1532 (JTAG) Interface
    – IEEE 1149.1 JTAG Boundary Scan Test
• Flexible Logic Macrocell
    – D/T/Latch Configurable Flip-flops
    – 5 Product Terms per Macrocell, Expandable up to 40
    – Global and Individual Register Control Signals
    – Global and Individual Output Enable
    – Programmable Output Slew Rate with Low Output Drive
    – Programmable Open Collector Output Option
    – Maximum Logic Utilization by Burying a Register with a Combinatorial Output and Vice Versa
• Fully Green (RoHS Compliant)
• 10 µA Standby Current
• Power Saving Option During Operation Using PD1 and PD2 Pins
Programmable Pin-keeper Option on Inputs and I/Os
Programmable Schmitt Trigger Option on Input and I/O Pins
Programmable Input and I/O Pull-up Option
• Unused I/O Pins Can Be Configured as Ground (Optional)
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-lead and 100-lead TQFP
• Advanced Digital CMOS Technology
    – 100% Tested
    – Completely ReProgrammable
    – 10,000 Program/Erase Cycles
    – 20-year Data Retention
    – 2000V ESD Protection
    – 200 mA Latch-up Immunity
• Security Fuse Feature
• Hot-Socketing Supported

Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Outputs Can Be Configured for High or Low Drive
• Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell
• Three Global Clock Pins
• Fast Registered Input from Product Term
• Pull-up Option on TMS and TDI JTAG Pins
• OTF (On-the-Fly) Reconfiguration Mode
• DRA (Direct Reconfiguration Access)

Компоненты Описание : High Performance E2PROM CPLD

Description
The ATF1502AS is a high-performance, high-density complex Programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502AS’s enhanced routing switchmatrices increase usable gate count and the odds of successful pin-locked design modifications.

Features
• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device
   – 32 Macrocells
   – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
   – 44 Pins
   – 7.5 ns Maximum Pin-to-pin Delay
   – Registered Operation up to 125 MHz
   – Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
   – D/T Latch Configurable Flip-flops
   – Global and Individual Register Control Signals
   – Global and Individual Output Enable
   – Programmable Output Slew Rate
   – Programmable Output Open Collector Option
   – Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
• Automatic 10 µA Standby for “L” Version
• Pin-controlled 1 mA Standby Mode
Programmable Pin-keeper Inputs and I/Os
• Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-lead PLCC and TQFP
• Advanced EEPROM Technology
   – 100% Tested
   – Completely ReProgrammable
   – 10,000 Program/Erase Cycles
   – 20-year Data Retention
   – 2000V ESD Protection
   – 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• Security Fuse Feature
• Green (Pb/Halide-fee/RoHS Compliant) Package Options

Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• D Latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (“L” Versions)
• Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
• VCCPower-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
   – Input Transition Detection
   – Power-down (“L” Versions)
   – Individual Macrocell Power Option
   – Disable ITD on Global Clocks, Inputs and I/O

Motorola
Motorola => Freescale
Компоненты Описание : QUAD Programmable OEPRATIONAL AMPLIFIER / QUAD Programmable COMPARATOR / Programmable DUAL OP AMP/DUAL COMPARATOR

QUAD Programmable OEPRATIONAL AMPLIFIER / QUAD Programmable COMPARATOR / Programmable DUAL OP AMP/DUAL COMPARATOR

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