DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset.
FEATURES • Generates 12-output buffers from one input. • Supports up to 2 DDR DIMMS or 3 SDRAM DIMMS. • Supports 266MHz DDR SDRAM. • One additional output for feedback. • Less than 5ns delay. • Skew between any outputs is less than 100 ps. • 2.5V or 3.3V Supply range. • Enhanced DDR and SDRAM Output Drive selected by I2C. • Available in 28 pin SSOP.
This INFINEON module is an industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which is organised as 64Mx64 high speed array in two memory banks designed for use in non-parity applications. These SO-DIMMs use back side protected P-TFBGA package technology. Decoupling capacitors are mounted on the board.
• u144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for notebook applications • Two bank 64M x 64 non-parity module organisation • suitable for use in PC100 and PC133 applications • Performance:
• Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Uses sixteen 256Mbit SDRAM (32MB x8 ) components in P-TFBGA packages • 8196 refresh cycles every 64 ms • Gold contact pad, JEDEC MO-190 outline dimensions • This module family is fully pin and functional compatible with the latest INTEL SO-DIMM specification • Importante Notice: This SO-DIMM module is based on 256Mbit SDRAM technology and can be used in applications only, where 256Mbit addressing is supported.
GENERAL DESCRIPTION The W83L177R is a 10 outputs SDRAM clock buffer for 2-DIMMs models incorporate with W83L197R-16 which is the clock synthesizer especially for the 100MHz models such as Intel BX chipsets.(Refer the datasheet fo Winbond W83L197R-16) The W83L177R receives the clock from chipset by the Buffer_In pin and provides almost zerodelay (less than 4ns propagation delay) SDRAM buffer outputs for the 10 SDRAM clocks which are synchronous with the CPU clock outputs priovided by W83L197R-16. The clock skew between any two clock outputs is less than 250ps and the output buffer impedance is about 15 ohms. The W83L177R also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs.
PRODUCT FEATURES ● 10 SDRAM clocks for 2-DIMMs ● Clock skew less than 250ps ● Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay) ● I2C 2-wire serial interface ● Programmable registers to enable/stop each output ● Incorporate with W83L197R-16 ● 28pin-SOP package (209mil)
DESCRIPTION The WED3DG644V is a 4Mx64 synchronous DRAM module which consists of four 4Mx16 SDRAM components in TSOP II package, and one 2Kb EEPROM in an 8 pin TSOP package for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate.
FEATURES ■ PC100 and PC133 compatible ■ Burst Mode Operation ■ Auto and Self Refresh capability ■ LVTTL compatible inputs and outputs ■ Serial Presence Detect with EEPROM ■ Fully synchronous: All signals are registered on the positive edge of the system clock ■ Programmable Burst Lengths: 1, 2, 4, 8 or Full Page ■ 3.3V ± 0.3V Power Supply ■ 144 Pin SO-DIMM JEDEC • D1: 27.94 (1.10”)
The V380SDC High Performance SDRAM Controller provides all aspects of SDRAM control for high performance embedded systems. The V380SDC enables system designers to replace many lower integration support components with a single, high-integration device. This saves design time, board space, and manufacturing cost.
The V380SDC from V3 Semiconductor provides the necessary (Enhanced) SDRAM access protocol and bus timing resources to work with the latest (E)SDRAM devices. The processor interface on the V380SDC implements the bus protocol of many popular RISC CPUs (AM29030/40, PowerPC 401 Gx, IDT 79RC32364, i960 Cx/Hx/Jx/Rx/Vx, M68040, 68K/ColdFire, PowerPC 750/60x). The V380SDC is also fully compatible with the EPC family of PCI bridges available from V3 Semiconductor.
Product Description/Features: • Low skew, Zero Delay Buffer • 1 to 13 SDRAM PC133 clock distribution • 1 to 6 pairs of DDR clock distribution • I2C for functional and output control • Separate feedback path for both memory mode to adjust synchronization. • Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs • Frequency support for up to 200MHz • Individual I2C clock stop for power mananagement • CMOS level control signal input
Recommended Application: DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/650 & 735/740/746 style chipsets.
Product Description/Features: • Low skew, fanout buffer • 1 to 12 differential clock distribution • I2C for functional and output control • Feedback pin for input to output synchronization • Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2 DDR DIMMs • Frequency supports up to 200MHz (DDR400) • Supports Power Down Mode for power mananagement • CMOS level control signal input
Switching Characteristics: • OUTPUT - OUTPUT skew: <100ps SDRAM OUTPUT - OUTPUT skew: <150ps DDR • Output Rise and Fall Time for DDR outputs: 600ps - 950ps • DUTY CYCLE: 47% - 53% DDR DUTY CYCLE: 45%- 55% SDRAM
The W83178S is a 13 outputs SDRAM clock buffer for 3-DIMMs models incorporate with W83196S-14 which is the clock synthesizer especially for the 100 MHz models such as Intel BX chipsets. (Refer the datasheet fo Winbond W83196S-14)