Block Diagram
O SC2 O SC1
O s c illa to r
D iv id e r
D IN
B u ffe r
D a ta D e te c to r
S y n c . D e te c to r
C o m p a ra to r
HT604L/HT614/HT692
D a ta S h ift
R e g is te r
L a tc h C ir c u it
D a ta
C o m p a ra to r
C o n tr o l L o g ic
T r a n s m is s io n G a te C ir c u it
B u ffe r
VT
A d d re s s
VDD VSS
Note: The address/data pins are available in various combinations (refer to the address/data table).
Pin Assignment
Latch Series
1 0 -A d d re s s
4 -D a ta
A 11 1
D 12 2
D 13 3
D 14 4
D 15 5
VT 6
D IN 7
O SC2 8
O SC1 9
V S S 10
20 V D D
19 A 9
18 A 8
17 A 7
16 A 6
15 A 4
14 A 3
13 A 2
12 A 1
11 A 0
H T604L
2 0 D IP -A /S O P -A
Momentary Series
1 0 -A d d re s s
4 -D a ta
A 11 1
D 12 2
D 13 3
D 14 4
D 15 5
VT 6
D IN 7
O SC2 8
O SC1 9
V S S 10
20 V D D
19 A 9
18 A 8
17 A 7
16 A 6
15 A 4
14 A 3
13 A 2
12 A 1
11 A 0
H T614
2 0 D IP -A /S O P -A
1 0 -A d d re s s
2 -D a ta
A 11 1
A 12 2
D 14 3
D 15 4
VT 5
D IN 6
O SC2 7
O SC1 8
VSS 9
18 V D D
17 A 9
16 A 8
15 A 7
14 A 6
13 A 3
12 A 2
11 A 1
10 A 0
H T692
1 8 D IP -A
Pin Description
Pin Name I/O
A0~A12
I
D10~D17
O
DIN
I
VT
O
OSC1
I
OSC2
O
VSS
¾
VDD
¾
Internal
Connection
TRANSMISSION
GATE
CMOS OUT
CMOS IN
CMOS OUT
OSCILLATOR
OSCILLATOR
¾
¾
Description
Input pins for address A0~A12 setting
They can be externally set to VDD, VSS or left open.
Output data pins
Serial data input pin
Valid transmission, active high
Oscillator input pin
Oscillator output pin
Negative power supply, ground
Positive power supply
Rev. 1.10
2
January 24, 2003