HA13561F
for Vps
Vsd2 =
1+
R103
R104
• Vth3
[V]
(12)
Vhys2 =
1+
R103
R104
• Vhyspm
[V]
(13)
where, Vth3, Vth4: Threshold voltage on pin 37 and pin 76 [V] (= 1.39)
Vhyspm: Hysteresis voltage on pin 37 and pin 76 [mV] (= 40)
Shut down voltage Vsd1, Vsd2 can be designed by the following range.
Vsd1 ≥ 4.25 [V], Vsd2 ≥ 10 [V]
8. The delay time tDLY of POR for power on reset is determined as follows.
tDLY =
C106 • Vth5
ICH3
[s]
(14)
where, Vth4: Threshold voltage on pin 38 [V] (= 1.4)
ICH3: Charge current on pin 38 [µA] (= 10)
9. The differential voltage (Vctl – V ) REF1 using for control of VCM driver depend on PWMDAC inputs
LSB, MSB as follows.
Vctl – VREF1 = 2 • VREF1 •
DPWM – 50
100
•
R6
R5
• HFLT(s)
(15)
where, DPWM:
(17)
HFLT(S):
Duty cycle on PWMIN [%]
Transfer function from pin 62 (PWMOUT) to pin 64 (Vctl) as shown in equation
To be satisfied with above equation (15), it is notice that the ratio of R6 to R7 must be choosen as
shown below.
R8 = 2 • R6 • 1
R7
R5
1
–
R6
R5
(16)
HFLT(s)
=
1
1+s•
C5 • R// – C3 • (R// + R3) •
R6
R5
+ C4 • (R// + R3 + R4)
+ s2 •
C5 • C4 • R// • (R3 + R4) – C5 • C3 • R// • R3 •
R6
R5
+ C3 • C4 • R4 • (R// + R3)
+ s3 • C3 • C4 • C5 • R// • R3 • R4
(17)
R// = R7 • R8
where,
R7 • R8
(18)
If you choose the R// << R3, then equation (17) can be simplified as following equation.
HFLT(s)
=
1
1
+
s
ωO
•
1
1 +2 • ζ •
s
ωn
+
s
ωn
2
(19)
15