EOL Data Sheet
ADDRESSES
CE#
OE#
WE#
DQ6
TCE
TOEH
TOE
16 Mbit Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
TWO READ CYCLES
WITH SAME OUTPUTS
TBR
VALID DATA
1249 F08.0
FIGURE 11: TOGGLE BIT TIMING DIAGRAM
ADDRESSES
SIX-BYTE CODE FOR CHIP-ERASE
555
2AA
555
555
2AA
555
TSCE
CE#
OE#
WE#
RY/BY#
TWP
TBY
TBR
DQ15-0
XXAA XX55
XX80
XXAA
XX55
XX10
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals
are interchageable as long as minimum timings are met. (See Table 14)
X can be VIL or VIH, but no other value.
FIGURE 12: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc.
20
VALID
1249 F09.1
S71249-07-EOL
02/08