Philips Semiconductors
8-stage shift-and-store bus register
Product specification
74LV4094
FUNCTION TABLE
INPUTS
CP
OE
STR
↑
L
X
↓
L
X
↑
H
L
↑
H
H
↑
H
H
↓
H
H
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
NC = no change
TIMING DIAGRAM
CLOCK INPUT
CP
DATA INPUT
D
STROBE INPUT
STR
OUTPUT ENABLE INPUT
OE
INTERNAL Q’0 (FF0)
OUTPUT
QP0
INTERNAL Q’6 (FF6)
OUTPUT
QP6
SERIAL OUTPUT
QS1
SERIAL OUTPUT
QS2
PARALLEL OUTPUT
SERIAL OUTPUTS
D
QP0
QPn
QS1
QS2
X
Z
Z
Q’6
NC
X
Z
Z
NC
QP7
X
NC
NC
Q’6
NC
L
L
QPn–1
Q’6
NC
H
H
QPn–1
Q’6
NC
H
NC
NC
NC
QP7
↑ = LOW-to–HIGH CP transition
↓ = HIGH-to-LOW CP transition
Q’6 = the information in the 8th register stage is transferred to the
8th register stage and QSn clock edge.
Z–state
Z–state
SV01616
1998 Jun 23
4