LC75854E, 75854W
Blocks that are reset
3. Output pin states during the reset period
Output pin
State during reset
S1/P1 to S4/P4
L*5
S5 to S39
L
COM1 to COM4
L
KS1/S40, KS2/S41
L*5
KS3 to KS5
!*6
KS6
H
DO
H*7
!: Don’t care
Note: * 5. These output pins are forcibly set to the segment output function and held low.
* 6. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
* 7. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset
period even if a key data read operation is performed.
No. 5066-18/25