I2C BUS Logic System
No.
Item
1 High level input voltage
2 Low level input voltage
3
Low level output voltage
SDA during current inflow of 3mA
4 Maximum clock frequency
5 Minimum waiting time for data change
6 Minimum waiting time for data transfer start
7 Low level clock pulse width
8 High level clock pulse width
9 Minimum waiting time for start preparation
10 Minimum data hold time
11 Maximum data preparation time
12 Rise time
13 Fall time
14 Minimum waiting time for stop preparation
CXA2153S
Symbol
Min.
Typ.
Max. Unit
VIH
3.0
—
5.0
V
VIL
0
—
1.5
V
VOL
0
—
0.4
V
fSCL
0
—
400 kHz
tBUF
1.3
—
—
µs
tHD; STA
0.6
—
—
µs
tLOW
1.3
—
—
µs
tHIGH
0.6
—
—
µs
tSU; STA
0.6
—
—
µs
tHD; DAT
0
—
900 ns
tSU; DAT
100
—
—
ns
tR
—
—
1
µs
tF
—
—
300 ns
tSU; STO
0.6
—
—
µs
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