Philips Semiconductors
Octal D-type flip-flop with reset;
positive-edge trigger
Product specification
74AHC273; 74AHCT273
SYMBOL PARAMETER
TEST CONDITIONS
WAVEFORMS CL
Tamb (°C)
25
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH propagation delay see Figs 6 and 9 15 pF −
CP to Qn
4.2 9.0
tPHL
propagation delay see Figs 7 and 9
MR to Qn
−
3.7 8.5
fmax
maximum clock
pulse frequency
120 165 −
1.0 10.5 1.0 11.5 ns
1.0 10.0 1.0 11.0 ns
100 −
100 −
ns
tPHL/tPLH propagation delay see Figs 6 and 9 50 pF −
CP to Qn
6.0 11.0 1.0 12.5 1.0 14.0 ns
tPHL
propagation delay see Figs 7 and 9
MR to Qn
−
5.3 10.5 1.0 12.0 1.0 13.5 ns
tW
clock pulse width see Figs 6 and 9
HIGH or LOW
5.0 −
−
5.0 −
5.0 −
ns
master reset
see Figs 7 and 9
pulse width LOW
5.0 −
−
5.0 −
5.0 −
ns
trem
removal time
MR to CP
2.0 −
−
2.0 −
2.0 −
ns
tsu
set-up time
see Figs 8 and 9
Dn to CP
th
hold time
Dn to CP
fmax
maximum clock
pulse frequency
3.0 −
−
3.0 −
3.0 −
ns
1.0 −
−
1.0 −
1.0 −
ns
80 110 −
70 −
70 −
ns
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
1999 Sep 01
10