E
28F016XD FLASH MEMORY
4.3 28F016XD—Enhanced Command Bus Definitions
Command
Read Extended Status Register
Lock Block/Confirm
Upload Status Bits/Confirm
Notes
1
First Bus Cycle
Oper Addr Data(3)
Write
X
xx71H
Write
X
xx77H
2
Write
X
xx97H
Second Bus Cycle
Oper Addr Data(3)
Read RA GSRD
BSRD
Write
BA xxD0H
Write
X
xxD0H
ADDRESS
DATA
BA = Block Address
AD = Array Data
RA = Extended Register Address
BSRD = BSR Data
PA = Program Address
GSRD = GSR Data
X = Don’t Care
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 4 for the Extended Status Register memory map.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. The upper byte of the data bus (D8–15) during command writes is a “Don’t Care.”
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