Timing Diagrams (Continued)
WRITE DISABLE CYCLE (WDS)
tCS
CS
SK
1 0 0 A5 A4
A1 A0
DI
Start Opcode
Address
Bit Bits(2)
Bits(6)
High - Z
DO
93C06:
Address bits pattern -> 0-0-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
tCS
CS
SK
1 0 1 A5 A4
A1 A0 D15 D14
D1 D0
DI
Start Opcode
Address
Data
Bit Bits(2)
Bits(6)
Bits(16)
High - Z
DO
93C06:
Address bits pattern -> 0-0-A3-A2-A1-A0; (A3-A0 -> User defined)
Data bits pattern -> User defined
tWP
Ready
Busy
WRITE ALL CYCLE (WRALL)
tCS
CS
SK
1 0 0 A5 A4
A1 A0 D15 D14
D1 D0
DI
Start Opcode
Address
Data
Bit Bits(2)
Bits(6)
Bits(16)
High - Z
DO
93C06:
Address bits pattern -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits pattern -> User defined
tWP
Ready
Busy
FM93C06 Rev. C.1
9
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