JMicron’s JM20330is a single chip solution for serial and parallel ATA translation. It includes the Serial ATA PHY, Link, Transport, and Parallel ATA (application layer) controller. The Serial ATA physical, link, and transport layers are compliant to Serial ATA 1.0a. JM20330 supports 1.5GHz data rate.
The application layer supports both the ATA register command set and PACKET command set, which could drive both Hard Disk Drive and ATAPI Optical Storage such as CR-ROM, CD-RW, DVD-ROM, DVD-RW, etc. The Serial ATA and the Parallel ATA application layer support both host and device operation and can be configured through a single Pin.
The µPD78F0988A and 78F0988A(A) are products in the µPD780988 Subseries in the 78K/0 Series that have flash memory in the place of the internal ROM of the µPD780988. Flash memory can be written or erased electrically with the device mounted on the board. Therefore, the µPD78F0988A and µPD78F0988A(A) are ideal for evaluation in system development, small-scale production, or systems likely to be upgraded frequently.
GENERAL DESCRIPTION The Z86C63/64 microcontroller introduces a new level of sophistication to single-chip architecture. The Z86C63/64 is a member of the Z8 single-chip microcontroller family with 32 Kbytes of ROM and 256 bytes of RAM.
The Z86C63 is housed in a 40-Pin DIP, and a 44-Pin PLCC package, and is manufactured in CMOS technology. The ROMless Pin option is available on the 44-Pin version only. The Z86C64 is housed in a 64-Pin DIP, and a 68-Pin PLCC. Both versions of the Z86C64 have the ROMless Pin option, which allows both external memory and preprogrammed ROM, enabling this Z8 microcontroller to be used in highvolume applications or where code flexibility is required. The Z86C96 ROMless Z8 will support the Z86C63/64.
Description The V82658B04S memory module is organized 8,388,608 x 64 bits in a 200 Pin memory module. The 8M x 64 memory module uses 4 Mosel-Vitelic 8M x 16 DDR SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
Features ■ JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module (SODIMM); 8,388,608 x 64 bit organization. ■ Utilizes High Performance 8M x 16 DDR SDRAM in TSOPII-66 Packages ■ Single +2.5V (± 0.2V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are SSTL-2 Compatible ■ 4096 Refresh Cycles every 64 ms ■ Serial Presence Detect (SPD) ■ DDR SDRAM Performance
The SMSC LPC47N217 is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The LPC47N217 implements the LPC interface, a Pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in Pins used. The part also includes 14 GPIO Pins.
The LPC47N217 incorporates a 16C550A compatible UART and one Multi-Mode parallel port with ChiProtect™ circuitry plus EPP and ECP support. This device also offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI CLKRUN# support, relocatable configuration ports, and three DMA channel options.