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LMU112 Даташит

Номер в каталогеКомпоненты Описаниепроизводитель
LMU112 12 x 12-bit Parallel Multiplier Logic-Devices
LOGIC Devices Logic-Devices
Other PDF  not available.
LMU112 image

The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K.

❑ 25 ns Worst-Case Multiply Time
❑ Low Power CMOS Technology
❑ Replaces Fairchild MPY112K
❑ Two’s Complement or Unsigned Operands
❑ Three-State Outputs
❑ Package Styles Available:
    • 48-pin PDIP
    • 52-pin PLCC, J-Lead


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